Method of modeling circuit cells with distributed serial loads

ABSTRACT

A plurality of serially coupled circuit cells ( 12-20 ) are modeled as a distributed serial load. The distributed serial load provides an accurate load model in situations where one cell is effected by loading on subsequent circuit cells, i.e. downstream loading is conveyed back to the first cell. The capacitance ( 22 ) and resistance ( 24 , of each cell has a loading effect on each previous cell. The effective resistance and capacitive values of each cell is identified and maintained as one element of the distributed serial load model. The distributed serial load accurately models the loading of unbuffered cells ( 16-20 ). The distributed serial load is also applicable to portions of circuit cells ( 38,40 ) that are not be buffered and where the downstream loading has an effect on previous circuit drivers ( 14 ).

BACKGROUND OF THE INVENTION

The present invention relates in general to circuit simulation and, moreparticularly, to a method of modeling a plurality of serially coupledcircuit cells with a distributed serial load.

Integrated circuit designs are becoming more complex while the timeallocated for the design effort is decreasing. To satisfy theseconflicting concerns, circuit designers are turning to libraries ofstandard cells from which to build the overall design. A standard cellis a pre-designed and pre-tested functional block that can be pluggedinto a circuit. The standard cell library includes a myriad offunctional blocks such NAND and NOR gates, multiplexers, memories,counters, multipliers, flipflops, etc. The standard cell can be assimple as an inverter and as complex as an arithmetic logic unit. Thus,standard cell libraries of pre-defined circuit functions are thebuilding blocks for more complex circuits. Building the circuit withcells from a library is very efficient especially for ASICs or otherstandard cell designs.

The library typically includes simulation data for each standard cell.The simulation data characterizes the standard cell by parameters suchas manufacturing process, supply voltage, temperature, edge transitionrate, and output load. The characterization parameters are useful whenrunning a computer aided design (CAD) simulation such as SPICE to testthe various features before a physical embodiment is built. The SPICEsimulator solves a number of voltage and current equations to determinethe performance of the cell. Each equation is a function of many othervoltages and currents in other nodes and transistors. The integratedcircuit is thus mathematically modeled in the computer simulator wherebythe design parameters are verified or manipulated to work out theinevitable problems associated with different embodiments beforeproceeding with the cost and effort of building an actual circuit.

Characterizing the output load of the cell is an important concern ofthe present invention. In the prior art, the output load of a cell istypically modeled by placing a single lumped capacitor at the output ofthe cell. The lumped capacitor models the effective capacitive load,e.g. number of devices being driven, as seen by the output driver of thecell. A common design rule for standard cell construction is to buffereach and every input and output of the cell. The buffering assures thatthe output of any cell is loaded by no more than the input buffer of thenext cell(s). The output load of one buffer is unaffected by any outputload of any cell it is driving. Unfortunately, a lumped effectivecapacitive load does not accurately model situations where the outputload of one cell is influenced by the load on subsequent cells. Forexample, if a first circuit cell drives a second circuit cell that hasno buffered input and no buffered output, then the loading on the outputof the second circuit cell has an effect on the output load of the firstcircuit cell. A single lumped capacitor does not accurately model suchunbuffered cells that do have an influence on the prior cells.

Hence, a need exists to accurately model circuit cells where the outputload is influenced by the load on subsequent unbuffered cells.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a plurality of serially coupledcircuit cells;

FIG. 2 is a block diagram illustrating a plurality of circuit cellsmodeled with a distributed serial load;

FIG. 3 is a block diagram illustrating a memory array;

FIG. 4 is a schematic diagram illustrating one bit cell of the memoryarray of FIG. 3; and

FIG. 5 illustrates an alternate distributed serial load withtransmission gates in the circuit cells.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, a circuit cell 12 provides a predetermined logicfunction such as a NAND or NOR gate, inverter, flipflop, multiplexer,memory, counter; arithmetic logic unit, etc. Cell 12 includes an outputbuffer 14 that drives serially coupled circuit cell 16, circuit cell 18and circuit cell 20. The prior art generally requires that the input andoutput of each cell include a buffer to isolate it from any cell otherthan an adjacent cell. Thus, if the output of cell 16 is buffered, thenbuffer 14 in cell 12 is not effected by the loading of cell 18 or cell20. The requirement to buffer the input and output of each cell is ofteninefficient and leads to unnecessary complexity and excessive circuitsimulation times. In many applications, it is necessary to have aplurality of serially coupled cells, such as cells 16, 18, and 20, whereeach cell has a loading effect on cell 12. That is, with the input andoutput of each cell unbuffered, buffer 14 becomes serially loaded by thecombination of cell 16, cell 18, and cell 20. The serially loadingcannot be accurately modeled by placing a single lumped capacitor at theoutput of buffer 14 in cell 12.

As a feature of the present invention, the loading on circuit cell 12 ismodeled as a distributed network of serial loads. In one embodimentshown in FIG. 2, cell 16 is modeled with an RC network of capacitor 22and resistor 24 that together represent the effective load impedance ofcell 16. Capacitor 22 is coupled between an input node of cell 16 and aground conductor. Resistor 24 is coupled between the input node of cell16 and its output node. Cell 18 is modeled with an RC network ofcapacitor 26 and resistor 28 that together represent the effective loadimpedance of cell 18. Capacitor 26 is coupled between an input node ofcell 18 and the ground conductor. Resistor 28 is coupled between theinput node of cell 18 and its output node. Cell 20 is modeled with an RCnetwork of capacitor 30 and resistor 32 that together represent theeffective load impedance of cell 20. The output of last cell in theserial chain is coupled to load termination buffer 34. The impedance ofthe distributed network provides an accurate load model for cell 12 incases where the input and output of cells 16-20 are unbuffered andtransparent, and therefore influence the loading on buffer 14. Thedistributed serial load of cells 16-20 allows the loading effect to beevaluated at the output of buffer 14 in cell 12, at the output of thelast cell in the serial chain, i.e. cell 20, and at the output oftermination buffer 34. Additional serial loads can be appended to theserial chain after cell 20. The number of serial loads on the output ofcell 12 is a function of the circuit design. A circuit simulator, whichis typically a computer program such as SPICE running on a computerworkstation, simulates the loading behavior and dynamics on buffer 14with the distributed serial loads 22-32 representing the load model.

The distributed serial load characteristic model is also applicablewithin a particular cell. In FIG. 3, circuit cell 16 is shown as memoryarray 36 with a plurality of bit cells. Buffer 14 in cell 12 drivesWORDLINE0 in memory array 36. Bit cell 38 is responsive to WORDLINE0 forproviding BIT0 and {overscore (BIT0)}. Bit cell 40 is responsive toWORDLINE0 for providing BIT1 and {overscore (BIT1)}. Circuit cell 42includes buffer 44 for driving WORDLINE1. Bit cell 46 is responsive toWORDLINE1 for providing BIT0 and {overscore (BIT0)}, while bit cell 48is responsive to WORDLINE1 for providing BIT1 and {overscore (BIT1)}.Sense amplifier 50 receives BIT0 and {overscore (BIT0)} and providescomplementary data signals to first inputs of multiplexer 52. Senseamplifier 54 receives BIT1 and {overscore (BIT1)} and providescomplementary data signals to second inputs of multiplexer 52. Buffer 56in circuit cell 58 provides the COLUMN SELECT control signal tomultiplexer 52 to select either the data signals from sense amplifier 50or the data signals from sense amplifier 54 depending on the state ofCOLUMN SELECT. The outputs from multiplexer 52 are complementary datasignals BIT and {overscore (BIT)}. I/O cell 60 receives complementarydata signals BIT and {overscore (BIT)} and provides a data signal DATAas the output of cell 16.

Further detail of bit cell 38 is shown in FIG. 4 including transistor 64having a gate coupled to WORDLINE0 and a source coupled to {overscore(BIT0)}. Inverter 66 has an input coupled to the drain of transistor 64and an output coupled to an input of inverter 68 and to the drain oftransistor 70. The output of inverter 68 is coupled to the drain oftransistor 64. Transistor 70 has a gate coupled to WORDLINE0 and asource coupled to {overscore (BIT0)}. Bit cells 40, 46, and 48 follow asimilar construction as bit cell 38.

To store a value BIT0=1and {overscore (BIT0)}=0in bit cell 38, BIT0 isdriven with a logic one and {overscore (BIT0)} is driven with a logiczero. Buffer 14 sets WORDLINE0 to logic one to turn on transistors 64and 70 which in turn drive the values BIT0=1 and {overscore (BIT0)}=0onto inverters 66 and 68. When WORDLINE0 returns to logic zero, theoutput of inverter 66 latches to logic zero and the output of inverter68 latches to logic one. To retrieve the contents of bit cell 38, BIT0and {overscore (BIT0)} are typically precharged to a logic one and thenallowed to float in a high impedance state. Buffer 14 sets WORDLINE0 tologic one to turn on transistor 64 and transistor 70 which in turnallows the output of inverter 68 to drive BIT0 toward a logic one andthe output of inverter 66 to drive {overscore (BIT0)} toward a logiczero. Sense amplifier 50 senses the direction that BIT0 and {overscore(BIT0)} are being driven by inverters 66 and 68 and aids in completingthe transition. Buffer 56 sets COLUMN SELECT to logic zero to select thecomplementary data signals BIT0 and {overscore (BIT0)} from senseamplifier 50. I/O cell 60 converts the complementary data signals BITand {overscore (BIT)} to a single logic one DATA signal.

Returning to FIG. 3, memory array 36 can be arranged in a variety ofconfigurations of word widths and column lengths, e.g. 1024 rows by four8-bit words per row, or 512 rows by two 16-bit words per row. For anyparticular arrangement, the bit cells load the outputs of cells 12 and42. For example, the gales of transistors 64 and 70 in bit cell 38 andthe gates of transistors 64 and 70 in bit cell 40 present a capacitiveload on the output of buffer 14. The metal conductor WORDLINE0, whichcan have significant length in large memory arrays, also provides aresistive load on the output of buffer 14. When transistors 64 and 70are enabled, inverter 68 is loaded by the resistance of conductor BIT0and the capacitance of other bit cells on BIT0. Likewise, inverter 66 isloaded by the resistance on conductor {overscore (BIT0)} and thecapacitance of other bit cells on {overscore (BIT0)}.

In the prior art models, typically only a few common memory arrayarrangements are pre-characterized by placing a single lumped capacitoron the output of each buffer. Likewise, a single lumped capacitor isplaced on the output of each buffer in the bit cell. When a particularmemory configuration needed to be simulated, the closest memory arraypre-characterization is used as the best available data, although notnecessarily an accurate model. The lumped capacitors are inaccurateespecially in large memory arrays where the word lines and bit lineshave significant resistance because of the length of the conductors withcapacitive loads interspersed along the conductor.

In the present invention, WORDLINE0 is modeled with a distributed serialload. The capacitance of the gates of transistors 64 and 70 in bit cell38 is modeled as a first capacitor to ground potential similar tocapacitor 22 in FIG. 2. The resistance of the WORDLINE0 conductorbetween the output of buffer 14 in cell 12 and the tap point of the gateof transistor 70 in bit cell 38 on WORDLINE0 is modeled as a firstresistor similar to resistor 24 in FIG. 2. The first RC network 22-24 isidentified as a model of the load of bit cell 38 on buffer 14.

The capacitance of the gates of transistors 64 and 70 in bit cell 40 ismodeled as a second capacitor to ground potential similar to capacitor26 in FIG. 2. The resistance of the WORDLINE0 conductor between the tappoint of the gate of transistor 70 in bit cell 38 on WORDLINE0 and thetap point of the gate of transistor 70 in bit cell 40 is modeled as asecond resistor similar to resistor 28 in FIG. 2. The second RC network26-28 is identified as a model of the load of bit cell 40 on buffer 14.If there are 32 bit cells attached to WORDLINE0, then there arethirty-one sets of RC models with the 32nd one being a model of the bitcell. The 32nd model is the termination load, e.g. another bit cell.Thus, the load on buffer 14 is modeled as a distributed serial load asshown in FIG. 2 to more accurately represent the actual behavior of theload on WORDLINE0 for buffer 14 in memory array 36. The circuitsimulator characterizes the loading behavior and dynamics on buffer 14based on the distributed serial load 22-32 representing the load model.

In a similar manner, WORDLINE1 is modeled with a distributed serialload. The capacitance of the gates of transistors 64 and 70 in bit cell46 is modeled as a first capacitor to ground potential similar tocapacitor 22 in FIG. 2. The resistance of the WORDLINE1 conductorbetween the output of buffer 14 and the tap point of the gate oftransistor 70 in bit cell 46 on WORDLINE1 is modeled as a first resistorsimilar to resistor 24 in FIG. 2. The capacitance of the gates oftransistors 64 and 70 in bit cell 48 is modeled as a second capacitor toground potential similar to capacitor 26 in FIG. 2. The resistance ofthe WORDLINE1 conductor between the tap point of the gate of transistor70 in bit cell 46 on WORDLINE1 and the tap point of the gate oftransistor 70 in bit cell 48 is modeled as a second resistor similar toresistor 28 in FIG. 2.

The load on BIT0 is also modeled with a distributed serial load.Inverter 68 in bit cell 38 is taken as the output driver buffer. Thecapacitance of bit cell 46 on BIT0 is modeled as a capacitor to groundpotential similar to capacitor 22 in FIG. 2. The resistance of the BIT0conductor between the tap point of the source of transistor 64 in bitcell 38 on the BIT0 conductor and the tap point of the source oftransistor 64 in bit cell 46 on the BIT0 conductor is modeled as aresistor similar to resistor 24. For the {overscore (BIT0)} conductor,inverter 66 in bit cell 38 is assumed to be the output driver buffer.The capacitance of bit cell 46 on the {overscore (BIT0)} conductor ismodeled as a capacitor to ground potential similar to capacitor 22. Theresistance of the {overscore (BIT0)} conductor between the tap point ofthe source of transistor 70 in bit cell 38 on {overscore (BIT0)} and thetap point of the source oft transistor 70 in bit cell 46 on the BIT0conductor is modeled as a resistor similar to resistor 24. Thus, theload on inverters 66 and 68 in bit cell 38 is modeled as a distributedserial load as shown in FIG. 2 to more accurately represent the actualbehavior of the load on BIT0 and {overscore (BIT0)} for inverters 66 and68 in bit cell 38.

The BIT1 conductor is modeled as a distributed serial load. Inverter 68in bit cell 40 is taken as the output driver buffer. The capacitance ofbit cell 48 on BIT1 is modeled as a capacitor to ground potentialsimilar to capacitor 22. The resistance of the BIT1 conductor betweenthe tap point of the source of transistor 64 in bit cell 40 on BIT1 andthe tap point of the source of transistor 64 in bit cell 48 on BIT1 ismodeled as a resistor similar to resistor 24. For the {overscore (BIT1)}conductor, inverter 66 in bit cell 40 is taken as the output driverbuffer. The capacitance of bit cell 48 on {overscore (BIT1)} is modeledas a capacitor to ground potential similar to capacitor 22. Theresistance of the {overscore (BIT1)} conductor between the tap point ofthe source of transistor 70 in bit cell 40 on {overscore (BIT1)} and thetap point of the source of transistor 70 in bit cell 48 on {overscore(BIT1)} is modeled as a resistor similar to resistor 24. Thus, the loadon inverters 66 and 68 in bit cell 40 is modeled as a distributed serialload as shown in FIG. 2 to more accurately represent the actual behaviorof the load on BIT1 and {overscore (BIT1)} for inverters 66 and 68 inbit cell 40. The circuit cell is typically characterized along thelongest path, e.g. across WORDLINE0 and down {overscore (BIT1)}, for thelongest delay.

All possible configurations are characterized by a circuit simulator andthe results are stored in a database. When the end user selects aparticular memory size, the distributed serial load model is retrievedfrom the database as a characterization of the memory configuration. Thedistributed serial load model is useful in situations where the load onone cell, e.g. cell 12, is affected by output loading on subsequentcells, e.g. cells 16, 18, and 20. Cells 16-20 affect the loading on cell12 because the input and outputs of cells 16-20 are transparent andunbuffered. The distributed serial load model is also useful insituations where portions of a circuit, capacitance of the gates oftransistors 64 and 70 and resistance of conductors between bit cells,must be individually characterized as a distributed serial load for anaccurate load model.

In another embodiment of the present invention, a data path includes aplurality of transmission gates serially coupled as shown in FIG. 5.Data path 72 includes cells 16-20. Cell 16 includes transmission gate 74comprising n-channel and p-channel transistors with their drains andsources coupled together. Complementary control signals drive the gatesof the transistors in transmission gate 74. Cell 18 includestransmission gate 76 comprising n-channel and p-channel transistors withtheir drains and sources coupled together. Complementary control signalsdrive the gates of the transistors in transmission gate 76. Cell 20includes transmission gate 78 comprising n-channel and p-channeltransistors with their drains and sources coupled together Complementarycontrol signals drive the gates of the transistors in transmission gate78.

The data path typically must operate with signals switching very rapidlyTherefore transmission gates 74-76 are not buffered. The loading onbuffer 14 in cell 12 is thus effected by the loading on transmissiongate 74, and the loading on transmission gate 76, and the loading ontransmission gate 78. Since the circuit simulator typically already haspreviously stored the effective impedance, e.g. resistance andcapacitance, of each transmission gate, the distributed serial load canbe modeled as the transmission gates themselves.

By now it should be appreciated that the present invention provides adistributed serial load model of a plurality of serially coupled circuitcells. Since the design rules do not require the input and output ofeach cell to be buffered, the loading on one cell is effected by loadingon subsequent circuit cells, i.e. downstream loading is conveyed back tothe first cell. The resistance and capacitance of each cell has aloading effect on each previous cell. The effective load impedance ofthe unbuffered cells cannot be accurately modeled by a single lumpedcapacitor. The effective resistance and capacitive values of each cellis identified and maintained as one element of the distributed serialload model. The distributed serial load accurately models the loading ofunbuffered cells. The distributed serial load model is also applicableto portions of circuit cells that are not be buffered and where thedownstream loading has an effect on previous circuit drivers.

While specific embodiments of the present invention have been shown anddescribed, further modifications and improvements will occur to thoseskilled in the art. It is understood that the invention is not limitedto the particular forms shown and it is intended for the appended claimsto cover all modifications which do not depart from the spirit and scopeof this invention.

What is claimed is:
 1. A method of modeling loading of a plurality ofserially coupled circuit cells, comprising the steps of: identifyingeffective load impedances for each of the plurality of serially coupledcircuit cells where the circuit cells include active elements; andforming a distributed serial load with said effective load impedanceswhere said distributed serial load provides a load model of theplurality of serially coupled circuit cells.
 2. The method of claim 1wherein said step of identifying effective load impedances includes thestep of providing a first capacitance for a first one of the pluralityof serially coupled circuit cells.
 3. The method of claim 2 wherein saidstep of identifying effective load impedances further includes the stepof providing a first resistance for said first one of the plurality ofserially coupled circuit cells.
 4. The method of claim 3 wherein saidstep of providing a first capacitance includes the step of providingsaid first capacitance between an input node of said first one of theplurality of serially coupled circuit cells and a ground conductor. 5.The method of claim 4 wherein said step of providing a first resistanceincludes the step of providing said first resistance between said inputnode of said first one of the plurality of serially coupled circuitcells and an output node of said first one of the plurality of seriallycoupled circuit cells.
 6. The method of claim 5 wherein said step ofidentifying effective load impedances further includes the step ofproviding a second capacitance for a second one of the plurality ofserially coupled circuit cells.
 7. The method of claim 6 wherein saidstep of identifying effective load impedances further includes the stepof providing a second resistance for said second one of the plurality ofserially coupled circuit cells.
 8. The method of claim 7 wherein saidstep of providing a second capacitance includes the step of providingsaid second capacitance between an input node of said second one of theplurality of serially coupled circuit cells and said ground conductor.9. The method of claim 8 wherein said step of providing a secondresistor includes the step of providing said second resistance betweensaid input node of said second one of the plurality of serially coupledcircuit cells and an output node of said second one of the plurality ofserially coupled circuit cells.
 10. A method of simulatingcharacteristics of a plurality of serially coupled circuit cells,comprising the steps of: providing a first load for a first one of theplurality of serially coupled circuit cells where the circuit cellsinclude active elements; providing a second load for a second one of theplurality of serially coupled circuit cells where the circuit cellsinclude active elements; and forming a distributed serial load with saidfirst and second loads of said first and second ones of the plurality ofserially coupled circuit cells where said distributed serial loadprovides a characteristic load model of the plurality of seriallycoupled circuit cells.
 11. The method of claim 10 wherein said step ofproviding a first load includes the step of providing a firstcapacitance between an input node of said first one of the plurality ofserially coupled circuit cells and a ground conductor.
 12. The method ofclaim 11 wherein said step of providing a first load further includesthe step of providing a first resistance between said input node of saidfirst one of the plurality of serially coupled circuit cells and anoutput node of said first one of the plurality of serially coupledcircuit cells.
 13. The method of claim 11 wherein said step of providinga second load includes the steps of: providing a second capacitancebetween an input node of said second one of the plurality of seriallycoupled circuit cells and said ground conductor; and providing a secondresistance between said input node of said second one of the pluralityof serially coupled circuit cells and an output node of said second oneof the plurality of serially coupled circuit cells.
 14. A method ofsimulating characteristics of a plurality of serially coupled circuitcells, comprising the steps of: providing a first load for a first oneof the plurality of serially coupled circuit cells where the circuitcells include active elements, wherein said step of providing a firstload includes the step of providing a first transmission gate between aninput node of said first one of the plurality of serially coupledcircuit cells and an output node of said first one of the plurality ofserially coupled circuit cells; providing a second load for a second oneof the plurality of serially coupled circuit cells where the circuitcells include active elements; and forming a distributed serial loadwith said first and second loads of said first and second ones of theplurality of serially coupled circuit cells where said distributedserial load provides a characteristic load model of the plurality ofserially coupled circuit cells.
 15. The method of claim 14 wherein saidstep of providing a first load includes the step of providing a secondtransmission gate between an input node of said second one of theplurality of serially coupled circuit cells and an output node of saidsecond one of the plurality of serially coupled circuit cells.
 16. Amethod of modeling a memory array, comprising the steps of: providing afirst effective load impedance for a first bit cell of the memory arraysproviding a second effective load impedance for a second bit cell of thememory array, and forming a distributed serial load with said first andsecond effective load impedances of said first and second bit cellswhere said distributed serial load provides a characteristic load modelof the memory array.
 17. The method of claim 16 wherein said step ofproviding a first effective load impedance includes the step ofproviding a first capacitance between an input node of said first bitcell and a ground conductor.
 18. The method of claim 17 wherein saidstep of providing a first effective load impedance further includes thestep of providing a first resistance between said input node of saidfirst bit cell and an output node of said first bit cell.
 19. The methodof claim 18 wherein said step of providing a second effective loadimpedance includes the step of providing a second capacitance between aninput node of said second bit cell and said ground conductor.
 20. Themethod of claim 19 wherein said step of providing a second effectiveload impedance further includes the step of providing a secondresistance between said input node of said second bit cell and an outputnode of said second bit cell.